The semiconductor device formed by stacking plural semiconductor chips has been under development for the purpose of reducing the packaging density. The CoC (Chip-on-Chip) technique for flip-chip bonding the semiconductor chip onto the other one has been employed to reduce the packaging density.
Japanese Unexamined Patent Application Publication No. 2000-156461 discloses the following technique as shown in FIGS. 8 to 13. That is, the second semiconductor chip (numbered as 130 in the document) and the solder ball interposer (32 in the document) are flip-chip bonded (FCB) onto the semiconductor wafer (140 in the document), and then the second semiconductor chip is coated. The coating (34 in the document) is flattened to expose the surface of the solder ball interposer. The first semiconductor chip formed from the semiconductor wafer has the second semiconductor chip flip-chip bonded thereto and is coated to be connectable from the upper surface.
Japanese Unexamined Patent Application Publication No. 2004-146728 discloses the following technique. That is, the second semiconductor chip (numbered as 1 in the document) is flip-chip bonded onto the first semiconductor chip (2 in the document) to form the solder electrode (11 in the document) on the first semiconductor chip so as to be connectable to the outside at the position higher than the second semiconductor chip.
In the case where the second semiconductor chip is flip-chip bonded onto the first semiconductor chip for increasing the packaging density, it is difficult to satisfy the requirement to reduce the thickness of the second semiconductor chip to less than 100 μm due to difficulty in handling of the thin semiconductor chip from the wafer and the chip tray. In the case where the flip chip bonding (FCB) is performed with the Au (gold)-Au pressure bonding process, the following difficulty occurs in addition to the difficulty in handling of the semiconductor chip. That is, the thin semiconductor chip which has been pressure bonded causes the underfill material to flow to the upper surface of the semiconductor chip and to be further adhered to the bonding tool used for handling the semiconductor chip. Accordingly, it is difficult to reduce the thickness of the semiconductor chip used in the CoC technique for packaging the semiconductor chip through the FCB.
In the process disclosed in Japanese Unexamined Patent Application Publication No. 2000-156461 and Japanese Unexamined Patent Application Publication No. 2004-146728, the side surface of the first semiconductor chip is exposed, which may be damaged during the test or packaging to the interposer.